An integrated circuit (IC) comprises cells of similar and/or various sizes, and connections between the cells. A cell may include several pins interconnected by wires to pins of one or more other cells, An IC may comprise both standard cells and macro-cells (also referred to simply as “macros”). Sizes of typical macro-cells are much larger than the sizes of standard cells. Further, macro-cells may be viewed as “black boxes,” as the logic and electronic behavior of macro-cells are known, but the inside structural description may not be known
Design engineers design ICs by transforming circuit description of the ICs into geometric descriptions, called layouts. To create layouts, design engineers typically use electronic design automation (EDA) applications. These applications provide sets of computer-based tools for creating, editing, and analyzing design layouts.
EDA applications create layouts by using geometric shapes that represent different materials and devices on ICs. For instance, EDA tools commonly use rectangular lines to represent the wire segments that interconnect the IC components. These tools also represent electronic and circuit IC components as geometric objects with varying shapes and sizes. For example, macro-cells are typically represented using rectangular blocks of varying sizes.
The IC design process entails various operations. Some of the physical-design operations that EDA applications commonly perform to obtain the IC layouts are: (1) circuit partitioning, which partitions a circuit if the circuit is too large for a single chip; (2) floor planning, which finds the alignment and relative orientation of the circuit modules (e.g., macro-cells); (3) placement, which determines more precisely the positions of the circuit components; (4) routing, which completes the interconnects between the circuit components; and (5) verification, which checks the layout to ensure that it meets design and functional requirements.
During floor planning and placement, cells are placed within a layout area to optimize certain objectives such as total wire length. Standard cells often have the same height and need to be placed in specified rows. Macro-cell placement, on the other hand, is more flexible than standard cell placement because the locations of macro-cells are not restricted and the dimensions of macro-cells vary.
Conventional EDA applications provide graphical user interfaces (GUIs) that enable users to perform floor planning and placement in preparation of IC design layouts. The GUIs of conventional EDA applications often require users to manually place each macro-cell one by one within the layout area. However, there are two main problems with the manual approach.
First, the process is slow and inefficient. As the design becomes bigger and bigger, there may be thousands of macro-cells. Manually placing them one by one could take a significant amount of time.
Second, users may he unable to determine the best layout solution among a number of macro-cells, especially when the number of macros is more than four and each macro has a different size or shape. The layout solution space may be too large to explore manually.